High-Capacity Data Processing with FPGA-Based Multiplication Algorithms and the Design of a High-Speed LUT Multiplier

Kenan Baysal; Deniz Taşkın

doi:10.35377/saucis...1229353

EN

High-Capacity Data Processing with FPGA-Based Multiplication Algorithms and the Design of a High-Speed LUT Multiplier

Abstract

Encryption algorithms work with very large key values to provide higher security. In order to process high-capacity data in real-time, we need advanced hardware structures. Today, when compared to the previous designing methods, the required hardware solutions can be designed more easily by using Field Programmable Gate Array (FPGA). Over the past decade, FPGA speeds, capacities, and design tools have been improved. Thus, the hardware that can process data with high capacity can be designed and produced with lower costs. The purpose of this study is to create the components of a high-speed arithmetic unit that can process high-capacity data, which can also be used for FPGA encoding algorithms. In this study, multiplication algorithms were analyzed and high-capacity adders that constitute high-speed multiplier and look-up tables were designed by using Very High-Speed Integrated Circuit Hardware Description Language (VHDL). The designed circuit/multiplier was synthesized with ISE Design Suite 14.7 software. The simulation results were obtained through ModelSIM and ISIM programs.

Keywords

References

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Details

Primary Language

English

Subjects

Software Architecture

Journal Section

Research Article

Authors

Kenan Baysal ^*
0000-0002-2205-7185
Türkiye

Deniz Taşkın
0000-0001-7374-8165
Türkiye

Early Pub Date

December 27, 2023

Publication Date

December 31, 2023

Submission Date

January 4, 2023

Acceptance Date

November 7, 2023

Published in Issue

Year 2023 Volume: 6 Number: 3

DOI

https://doi.org/10.35377/saucis...1229353

IZ

https://izlik.org/JA99BW75UJ

Cite

RIS / Bibtex

APA

Baysal, K., & Taşkın, D. (2023). High-Capacity Data Processing with FPGA-Based Multiplication Algorithms and the Design of a High-Speed LUT Multiplier. Sakarya University Journal of Computer and Information Sciences, 6(3), 208-217. https://doi.org/10.35377/saucis...1229353

AMA

1.Baysal K, Taşkın D. High-Capacity Data Processing with FPGA-Based Multiplication Algorithms and the Design of a High-Speed LUT Multiplier. SAUCIS. 2023;6(3):208-217. doi:10.35377/saucis.1229353

Chicago

Baysal, Kenan, and Deniz Taşkın. 2023. “High-Capacity Data Processing With FPGA-Based Multiplication Algorithms and the Design of a High-Speed LUT Multiplier”. Sakarya University Journal of Computer and Information Sciences 6 (3): 208-17. https://doi.org/10.35377/saucis. 1229353.

EndNote

Baysal K, Taşkın D (December 1, 2023) High-Capacity Data Processing with FPGA-Based Multiplication Algorithms and the Design of a High-Speed LUT Multiplier. Sakarya University Journal of Computer and Information Sciences 6 3 208–217.

IEEE

[1]K. Baysal and D. Taşkın, “High-Capacity Data Processing with FPGA-Based Multiplication Algorithms and the Design of a High-Speed LUT Multiplier”, SAUCIS, vol. 6, no. 3, pp. 208–217, Dec. 2023, doi: 10.35377/saucis...1229353.

ISNAD

Baysal, Kenan - Taşkın, Deniz. “High-Capacity Data Processing With FPGA-Based Multiplication Algorithms and the Design of a High-Speed LUT Multiplier”. Sakarya University Journal of Computer and Information Sciences 6/3 (December 1, 2023): 208-217. https://doi.org/10.35377/saucis. 1229353.

JAMA

1.Baysal K, Taşkın D. High-Capacity Data Processing with FPGA-Based Multiplication Algorithms and the Design of a High-Speed LUT Multiplier. SAUCIS. 2023;6:208–217.

MLA

Baysal, Kenan, and Deniz Taşkın. “High-Capacity Data Processing With FPGA-Based Multiplication Algorithms and the Design of a High-Speed LUT Multiplier”. Sakarya University Journal of Computer and Information Sciences, vol. 6, no. 3, Dec. 2023, pp. 208-17, doi:10.35377/saucis. 1229353.

Vancouver

1.Kenan Baysal, Deniz Taşkın. High-Capacity Data Processing with FPGA-Based Multiplication Algorithms and the Design of a High-Speed LUT Multiplier. SAUCIS. 2023 Dec. 1;6(3):208-17. doi:10.35377/saucis. 1229353