Zynq FPGA-Based Acceleration of Kernelized Correlation Filters via High-Level Synthesis of a Custom DFT Block

Mustafa Yetiş; Enver Çavuş

doi:10.35377/saucis...1402561

EN

Zynq FPGA-Based Acceleration of Kernelized Correlation Filters via High-Level Synthesis of a Custom DFT Block

Abstract

This study presents a hardware-software co-design implementation of an accelerator for the Kernelized Correlation Filter (KCF) tracking algorithm. Leveraging the High-level synthesis (HLS) and the Zynq heterogeneous platform, the KCF algorithm’s performance is enhanced by using a custom hardware implementation for the computationally intensive Discrete Fourier Transform (DFT) operation. Within this framework, a custom combined DFT and inverse DFT IP, named CDFT, is developed and optimized on the Programmable Logic (PL) side of the Xilinx ZCU102 FPGA, whereas the rest of the KCF algorithm is run with customized Petalinux build on the (Processing System) side. To assess real-world performance, a driver for the CDFT IP and a user application were created to measure metrics like Center Location Error (CLE), Intersection over Union (IoU), and Frame per Second (FPS). The designed DFT accelerator achieves a remarkable speedup of 21x compared to a software DFT implementation. At the algorithm level, the KCF accelerator obtains a 6x speed up with negligible precision loss. In comparison to prior studies employing exclusively hardware implementations, the proposed approach demonstrates a high accuracy at a moderate speed, while there exists potential for further optimizations to enhance its performance even further.

Keywords

References

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Details

Primary Language

English

Subjects

Software Engineering (Other)

Journal Section

Research Article

Authors

Mustafa Yetiş ^*
0009-0009-5887-6690
Türkiye

Enver Çavuş
0000-0002-7203-9700
Türkiye

Early Pub Date

April 27, 2024

Publication Date

April 30, 2024

Submission Date

December 9, 2023

Acceptance Date

January 15, 2024

Published in Issue

Year 2024 Volume: 7 Number: 1

DOI

https://doi.org/10.35377/saucis...1402561

IZ

https://izlik.org/JA52GN86ZH

Cite

RIS / Bibtex

APA

Yetiş, M., & Çavuş, E. (2024). Zynq FPGA-Based Acceleration of Kernelized Correlation Filters via High-Level Synthesis of a Custom DFT Block. Sakarya University Journal of Computer and Information Sciences, 7(1), 11-21. https://doi.org/10.35377/saucis...1402561

AMA

1.Yetiş M, Çavuş E. Zynq FPGA-Based Acceleration of Kernelized Correlation Filters via High-Level Synthesis of a Custom DFT Block. SAUCIS. 2024;7(1):11-21. doi:10.35377/saucis.1402561

Chicago

Yetiş, Mustafa, and Enver Çavuş. 2024. “Zynq FPGA-Based Acceleration of Kernelized Correlation Filters via High-Level Synthesis of a Custom DFT Block”. Sakarya University Journal of Computer and Information Sciences 7 (1): 11-21. https://doi.org/10.35377/saucis. 1402561.

EndNote

Yetiş M, Çavuş E (April 1, 2024) Zynq FPGA-Based Acceleration of Kernelized Correlation Filters via High-Level Synthesis of a Custom DFT Block. Sakarya University Journal of Computer and Information Sciences 7 1 11–21.

IEEE

[1]M. Yetiş and E. Çavuş, “Zynq FPGA-Based Acceleration of Kernelized Correlation Filters via High-Level Synthesis of a Custom DFT Block”, SAUCIS, vol. 7, no. 1, pp. 11–21, Apr. 2024, doi: 10.35377/saucis...1402561.

ISNAD

Yetiş, Mustafa - Çavuş, Enver. “Zynq FPGA-Based Acceleration of Kernelized Correlation Filters via High-Level Synthesis of a Custom DFT Block”. Sakarya University Journal of Computer and Information Sciences 7/1 (April 1, 2024): 11-21. https://doi.org/10.35377/saucis. 1402561.

JAMA

1.Yetiş M, Çavuş E. Zynq FPGA-Based Acceleration of Kernelized Correlation Filters via High-Level Synthesis of a Custom DFT Block. SAUCIS. 2024;7:11–21.

MLA

Yetiş, Mustafa, and Enver Çavuş. “Zynq FPGA-Based Acceleration of Kernelized Correlation Filters via High-Level Synthesis of a Custom DFT Block”. Sakarya University Journal of Computer and Information Sciences, vol. 7, no. 1, Apr. 2024, pp. 11-21, doi:10.35377/saucis. 1402561.

Vancouver

1.Mustafa Yetiş, Enver Çavuş. Zynq FPGA-Based Acceleration of Kernelized Correlation Filters via High-Level Synthesis of a Custom DFT Block. SAUCIS. 2024 Apr. 1;7(1):11-2. doi:10.35377/saucis. 1402561