Encryption algorithms work with very large key values to provide higher security. In order to process high-capacity data in real-time, we need advanced hardware structures. Today, when compared to the previous designing methods, the required hardware solutions can be designed more easily by using Field Programmable Gate Array (FPGA). Over the past decade, FPGA speeds, capacities, and design tools have been improved. Thus, the hardware that can process data with high capacity can be designed and produced with lower costs.
The purpose of this study is to create the components of a high-speed arithmetic unit that can process high-capacity data, which can also be used for FPGA encoding algorithms.
In this study, multiplication algorithms were analyzed and high-capacity adders that constitute high-speed multiplier and look-up tables were designed by using Very High-Speed Integrated Circuit Hardware Description Language (VHDL). The designed circuit/multiplier was synthesized with ISE Design Suite 14.7 software. The simulation results were obtained through ModelSIM and ISIM programs.
Birincil Dil | İngilizce |
---|---|
Konular | Yazılım Mimarisi |
Bölüm | Makaleler |
Yazarlar | |
Erken Görünüm Tarihi | 27 Aralık 2023 |
Yayımlanma Tarihi | 31 Aralık 2023 |
Gönderilme Tarihi | 4 Ocak 2023 |
Kabul Tarihi | 7 Kasım 2023 |
Yayımlandığı Sayı | Yıl 2023Cilt: 6 Sayı: 3 |
The papers in this journal are licensed under a Creative Commons Attribution-NonCommercial 4.0 International License