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Year 2023, Volume: 6 Issue: 3, 208 - 217, 31.12.2023

Kenan Baysal , Deniz Taşkın

https://doi.org/10.35377/saucis...1229353

Abstract

References

  • [1] R. W. Keyes., "Physical Limits of Silicon Transistors and Circuits", Reports on Progress in Physics, vol. 68, no. 12, 2005, doi: 10.1088/0034-4885/68/12/R01
  • [2] B. Parhami, Computer Arithmetic Algorithms and Hardware Designs Secon Edition, Oxford University Press, New York USA, 2010, ISBN 978-0-19-532848-6
  • [3] A. A. H. Abd-Elkader, M. Rashdan, E. A. M. Hasaneen and H. F. A. Hamed, "Efficient implementation of Montgomery modular multiplier on FPGA," Computers and Electrical Engineering, vol. 97, 2022, doi: https://doi.org/10.1016/j.compeleceng.2021.107585
  • [4] A. Behl, A. Gokhale, N. Sharma, "Design and Implementation of Fast Booth-2 Multiplier on Artix FPGA", Procedia Computer Science, vol. 173, pp. 140-148, 2020, doi: https://doi.org/10.1016/j.procs.2020.06.018
  • [5] R. K. Sakali, S. Veeramachaneni, N. M. Sk, "Preferential fault-tolerance multiplier design to mitigate soft errors in FPGAs", Integration, vol. 93, 2023, doi: https://doi.org/10.1016/j.vlsi.2023.102068
  • [6] L. Malathi, A. Bharathi, A.N. Jayanthi, "FPGA design of FFT based intelligent accelerator with optimized Wallace tree multiplier for image super resolution and quality enhancement", Biomedical Signal Processing and Control, vol. 88, part B, 2024, doi: https://doi.org/10.1016/j.bspc.2023.105599
  • [7] V. Bianchi, I. D. Munari, "A modular Vedic multiplier architecture for model-based design and deployment on FPGA platforms", Microprocessors and Microsystems, vol. 76, 2020, doi: https://doi.org/10.1016/j.micpro.2020.103106
  • [8] E. Özcan, S. S. Erdem, "A fast digit based Montgomery multiplier designed for FPGAs with DSP resources", Microprocessors and Microsystems, vol 62, pp. 12-19, 2018, doi: https://doi.org/10.1016/j.micpro.2018.06.015
  • [9] M. Morales-Sandoval, C. Feregrino-Uribe, P. Kitsos, R. Cumplido, "Area/performance trade-off analysis of an FPGA digit-serial GF(2m) Montgomery multiplier based on LFSR”, Computers & Electrical Engineering, vol. 32, i. 2, pp. 542-549, 2013, doi: https://doi.org/10.1016/j.compeleceng.2012.08.010
  • [10] R. S. Özbey and A. Sertbaş, "Klasik Çarpma Algoritmalarının Donanımsal Simülasyonları ve Performans Değerlendirimi", Inter. Conf. on Electrical and Electronics Engineering (ELECO 2004), pp. 303-308, 2004
  • [11] A. D. Booth, "A Signed Binary Multiplication Technique", The Quarterly Journal of Mechanics and Applied Mathematics. Math. Oxford University Press, vol. 4, no. 2, pp. 236-240, 1951, doi: https://doi.org/10.1093/qjmam/4.2.236
  • [12] C. S. Wallace, "A Suggestion for a Fast Multiplier", IEEE Transactions on Electronic Computers, vol. 13, no. 1, pp. 14-17, 1964, doi: 10.1109/PGEC.1964.263830
  • [13] M. R. Kumar and G. P. Rao, " Design and Implementation Of 32 Bit High Level Wallace Tree Multiplier", International Journal of Technical Research and Applications, vol. 1, no. 4, pp. 86 - 90, 2013, Accessed : 29 October 2023 [Online]. Available: https://api.semanticscholar.org/CorpusID:13022315
  • [14] J. Kulisz, J. Mikucki, "An IP-Core Generator for Circuits Performing Arithmetic Multiplication", IFAC Proceedings Volumes, vol. 46, i. 28, 2013, doi: https://doi.org/10.3182/20130925-3-CZ-3023.00006
  • [15] A. J. Al-Khalili, Digital Design and Synthesis Lecture Notes (2019), Accessed : 29 October 2023 [Online]. Available: https://users.encs.concordia.ca/~asim/COEN_6501/elec650.html
  • [16] S. Mishra and M. Pradhan, "Implementation of Karatsuba Algorithm Using Polynomial Multiplication", Indian Journal of Computer Science and Engineering, ISSN: 0976-5166, vol. 3, no. 1, pp 88 - 93, 2012.
  • [17] R. T. Kneusel, Numbers and Computers, Springer, USA, pp. 136, 2015, ISBN: 978-3-319-17260-6

High-Capacity Data Processing with FPGA-Based Multiplication Algorithms and the Design of a High-Speed LUT Multiplier

Year 2023, Volume: 6 Issue: 3, 208 - 217, 31.12.2023

Kenan Baysal , Deniz Taşkın

https://doi.org/10.35377/saucis...1229353

Abstract

Encryption algorithms work with very large key values to provide higher security. In order to process high-capacity data in real-time, we need advanced hardware structures. Today, when compared to the previous designing methods, the required hardware solutions can be designed more easily by using Field Programmable Gate Array (FPGA). Over the past decade, FPGA speeds, capacities, and design tools have been improved. Thus, the hardware that can process data with high capacity can be designed and produced with lower costs.
The purpose of this study is to create the components of a high-speed arithmetic unit that can process high-capacity data, which can also be used for FPGA encoding algorithms.
In this study, multiplication algorithms were analyzed and high-capacity adders that constitute high-speed multiplier and look-up tables were designed by using Very High-Speed Integrated Circuit Hardware Description Language (VHDL). The designed circuit/multiplier was synthesized with ISE Design Suite 14.7 software. The simulation results were obtained through ModelSIM and ISIM programs.

Keywords

FPGA VHDL look up table multiplication adder

References

  • [1] R. W. Keyes., "Physical Limits of Silicon Transistors and Circuits", Reports on Progress in Physics, vol. 68, no. 12, 2005, doi: 10.1088/0034-4885/68/12/R01
  • [2] B. Parhami, Computer Arithmetic Algorithms and Hardware Designs Secon Edition, Oxford University Press, New York USA, 2010, ISBN 978-0-19-532848-6
  • [3] A. A. H. Abd-Elkader, M. Rashdan, E. A. M. Hasaneen and H. F. A. Hamed, "Efficient implementation of Montgomery modular multiplier on FPGA," Computers and Electrical Engineering, vol. 97, 2022, doi: https://doi.org/10.1016/j.compeleceng.2021.107585
  • [4] A. Behl, A. Gokhale, N. Sharma, "Design and Implementation of Fast Booth-2 Multiplier on Artix FPGA", Procedia Computer Science, vol. 173, pp. 140-148, 2020, doi: https://doi.org/10.1016/j.procs.2020.06.018
  • [5] R. K. Sakali, S. Veeramachaneni, N. M. Sk, "Preferential fault-tolerance multiplier design to mitigate soft errors in FPGAs", Integration, vol. 93, 2023, doi: https://doi.org/10.1016/j.vlsi.2023.102068
  • [6] L. Malathi, A. Bharathi, A.N. Jayanthi, "FPGA design of FFT based intelligent accelerator with optimized Wallace tree multiplier for image super resolution and quality enhancement", Biomedical Signal Processing and Control, vol. 88, part B, 2024, doi: https://doi.org/10.1016/j.bspc.2023.105599
  • [7] V. Bianchi, I. D. Munari, "A modular Vedic multiplier architecture for model-based design and deployment on FPGA platforms", Microprocessors and Microsystems, vol. 76, 2020, doi: https://doi.org/10.1016/j.micpro.2020.103106
  • [8] E. Özcan, S. S. Erdem, "A fast digit based Montgomery multiplier designed for FPGAs with DSP resources", Microprocessors and Microsystems, vol 62, pp. 12-19, 2018, doi: https://doi.org/10.1016/j.micpro.2018.06.015
  • [9] M. Morales-Sandoval, C. Feregrino-Uribe, P. Kitsos, R. Cumplido, "Area/performance trade-off analysis of an FPGA digit-serial GF(2m) Montgomery multiplier based on LFSR”, Computers & Electrical Engineering, vol. 32, i. 2, pp. 542-549, 2013, doi: https://doi.org/10.1016/j.compeleceng.2012.08.010
  • [10] R. S. Özbey and A. Sertbaş, "Klasik Çarpma Algoritmalarının Donanımsal Simülasyonları ve Performans Değerlendirimi", Inter. Conf. on Electrical and Electronics Engineering (ELECO 2004), pp. 303-308, 2004
  • [11] A. D. Booth, "A Signed Binary Multiplication Technique", The Quarterly Journal of Mechanics and Applied Mathematics. Math. Oxford University Press, vol. 4, no. 2, pp. 236-240, 1951, doi: https://doi.org/10.1093/qjmam/4.2.236
  • [12] C. S. Wallace, "A Suggestion for a Fast Multiplier", IEEE Transactions on Electronic Computers, vol. 13, no. 1, pp. 14-17, 1964, doi: 10.1109/PGEC.1964.263830
  • [13] M. R. Kumar and G. P. Rao, " Design and Implementation Of 32 Bit High Level Wallace Tree Multiplier", International Journal of Technical Research and Applications, vol. 1, no. 4, pp. 86 - 90, 2013, Accessed : 29 October 2023 [Online]. Available: https://api.semanticscholar.org/CorpusID:13022315
  • [14] J. Kulisz, J. Mikucki, "An IP-Core Generator for Circuits Performing Arithmetic Multiplication", IFAC Proceedings Volumes, vol. 46, i. 28, 2013, doi: https://doi.org/10.3182/20130925-3-CZ-3023.00006
  • [15] A. J. Al-Khalili, Digital Design and Synthesis Lecture Notes (2019), Accessed : 29 October 2023 [Online]. Available: https://users.encs.concordia.ca/~asim/COEN_6501/elec650.html
  • [16] S. Mishra and M. Pradhan, "Implementation of Karatsuba Algorithm Using Polynomial Multiplication", Indian Journal of Computer Science and Engineering, ISSN: 0976-5166, vol. 3, no. 1, pp 88 - 93, 2012.
  • [17] R. T. Kneusel, Numbers and Computers, Springer, USA, pp. 136, 2015, ISBN: 978-3-319-17260-6
There are 17 citations in total.

Details

Primary Language English
Subjects Software Architecture
Journal Section Articles
Authors

Kenan Baysal 0000-0002-2205-7185

Deniz Taşkın 0000-0001-7374-8165

Early Pub Date December 27, 2023
Publication Date December 31, 2023
Submission Date January 4, 2023
Acceptance Date November 7, 2023
Published in Issue Year 2023 Volume: 6 Issue: 3

Cite

APA Baysal, K., & Taşkın, D. (2023). High-Capacity Data Processing with FPGA-Based Multiplication Algorithms and the Design of a High-Speed LUT Multiplier. Sakarya University Journal of Computer and Information Sciences, 6(3), 208-217. https://doi.org/10.35377/saucis...1229353
AMA Baysal K, Taşkın D. High-Capacity Data Processing with FPGA-Based Multiplication Algorithms and the Design of a High-Speed LUT Multiplier. SAUCIS. December 2023;6(3):208-217. doi:10.35377/saucis.1229353
Chicago Baysal, Kenan, and Deniz Taşkın. “High-Capacity Data Processing With FPGA-Based Multiplication Algorithms and the Design of a High-Speed LUT Multiplier”. Sakarya University Journal of Computer and Information Sciences 6, no. 3 (December 2023): 208-17. https://doi.org/10.35377/saucis. 1229353.
EndNote Baysal K, Taşkın D (December 1, 2023) High-Capacity Data Processing with FPGA-Based Multiplication Algorithms and the Design of a High-Speed LUT Multiplier. Sakarya University Journal of Computer and Information Sciences 6 3 208–217.
IEEE K. Baysal and D. Taşkın, “High-Capacity Data Processing with FPGA-Based Multiplication Algorithms and the Design of a High-Speed LUT Multiplier”, SAUCIS, vol. 6, no. 3, pp. 208–217, 2023, doi: 10.35377/saucis...1229353.
ISNAD Baysal, Kenan - Taşkın, Deniz. “High-Capacity Data Processing With FPGA-Based Multiplication Algorithms and the Design of a High-Speed LUT Multiplier”. Sakarya University Journal of Computer and Information Sciences 6/3 (December2023), 208-217. https://doi.org/10.35377/saucis. 1229353.
JAMA Baysal K, Taşkın D. High-Capacity Data Processing with FPGA-Based Multiplication Algorithms and the Design of a High-Speed LUT Multiplier. SAUCIS. 2023;6:208–217.
MLA Baysal, Kenan and Deniz Taşkın. “High-Capacity Data Processing With FPGA-Based Multiplication Algorithms and the Design of a High-Speed LUT Multiplier”. Sakarya University Journal of Computer and Information Sciences, vol. 6, no. 3, 2023, pp. 208-17, doi:10.35377/saucis. 1229353.
Vancouver Baysal K, Taşkın D. High-Capacity Data Processing with FPGA-Based Multiplication Algorithms and the Design of a High-Speed LUT Multiplier. SAUCIS. 2023;6(3):208-17.
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