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High-Capacity Data Processing with FPGA-Based Multiplication Algorithms and the Design of a High-Speed LUT Multiplier

Yıl 2023, Cilt: 6 Sayı: 3, 208 - 217, 31.12.2023

Kenan Baysal Deniz Taşkın

https://doi.org/10.35377/saucis...1229353

Öz

Encryption algorithms work with very large key values to provide higher security. In order to process high-capacity data in real-time, we need advanced hardware structures. Today, when compared to the previous designing methods, the required hardware solutions can be designed more easily by using Field Programmable Gate Array (FPGA). Over the past decade, FPGA speeds, capacities, and design tools have been improved. Thus, the hardware that can process data with high capacity can be designed and produced with lower costs.
The purpose of this study is to create the components of a high-speed arithmetic unit that can process high-capacity data, which can also be used for FPGA encoding algorithms.
In this study, multiplication algorithms were analyzed and high-capacity adders that constitute high-speed multiplier and look-up tables were designed by using Very High-Speed Integrated Circuit Hardware Description Language (VHDL). The designed circuit/multiplier was synthesized with ISE Design Suite 14.7 software. The simulation results were obtained through ModelSIM and ISIM programs.

Anahtar Kelimeler

FPGA VHDL look up table multiplication adder

Kaynakça

  • [1] R. W. Keyes., "Physical Limits of Silicon Transistors and Circuits", Reports on Progress in Physics, vol. 68, no. 12, 2005, doi: 10.1088/0034-4885/68/12/R01
  • [2] B. Parhami, Computer Arithmetic Algorithms and Hardware Designs Secon Edition, Oxford University Press, New York USA, 2010, ISBN 978-0-19-532848-6
  • [3] A. A. H. Abd-Elkader, M. Rashdan, E. A. M. Hasaneen and H. F. A. Hamed, "Efficient implementation of Montgomery modular multiplier on FPGA," Computers and Electrical Engineering, vol. 97, 2022, doi: https://doi.org/10.1016/j.compeleceng.2021.107585
  • [4] A. Behl, A. Gokhale, N. Sharma, "Design and Implementation of Fast Booth-2 Multiplier on Artix FPGA", Procedia Computer Science, vol. 173, pp. 140-148, 2020, doi: https://doi.org/10.1016/j.procs.2020.06.018
  • [5] R. K. Sakali, S. Veeramachaneni, N. M. Sk, "Preferential fault-tolerance multiplier design to mitigate soft errors in FPGAs", Integration, vol. 93, 2023, doi: https://doi.org/10.1016/j.vlsi.2023.102068
  • [6] L. Malathi, A. Bharathi, A.N. Jayanthi, "FPGA design of FFT based intelligent accelerator with optimized Wallace tree multiplier for image super resolution and quality enhancement", Biomedical Signal Processing and Control, vol. 88, part B, 2024, doi: https://doi.org/10.1016/j.bspc.2023.105599
  • [7] V. Bianchi, I. D. Munari, "A modular Vedic multiplier architecture for model-based design and deployment on FPGA platforms", Microprocessors and Microsystems, vol. 76, 2020, doi: https://doi.org/10.1016/j.micpro.2020.103106
  • [8] E. Özcan, S. S. Erdem, "A fast digit based Montgomery multiplier designed for FPGAs with DSP resources", Microprocessors and Microsystems, vol 62, pp. 12-19, 2018, doi: https://doi.org/10.1016/j.micpro.2018.06.015
  • [9] M. Morales-Sandoval, C. Feregrino-Uribe, P. Kitsos, R. Cumplido, "Area/performance trade-off analysis of an FPGA digit-serial GF(2m) Montgomery multiplier based on LFSR”, Computers & Electrical Engineering, vol. 32, i. 2, pp. 542-549, 2013, doi: https://doi.org/10.1016/j.compeleceng.2012.08.010
  • [10] R. S. Özbey and A. Sertbaş, "Klasik Çarpma Algoritmalarının Donanımsal Simülasyonları ve Performans Değerlendirimi", Inter. Conf. on Electrical and Electronics Engineering (ELECO 2004), pp. 303-308, 2004
  • [11] A. D. Booth, "A Signed Binary Multiplication Technique", The Quarterly Journal of Mechanics and Applied Mathematics. Math. Oxford University Press, vol. 4, no. 2, pp. 236-240, 1951, doi: https://doi.org/10.1093/qjmam/4.2.236
  • [12] C. S. Wallace, "A Suggestion for a Fast Multiplier", IEEE Transactions on Electronic Computers, vol. 13, no. 1, pp. 14-17, 1964, doi: 10.1109/PGEC.1964.263830
  • [13] M. R. Kumar and G. P. Rao, " Design and Implementation Of 32 Bit High Level Wallace Tree Multiplier", International Journal of Technical Research and Applications, vol. 1, no. 4, pp. 86 - 90, 2013, Accessed : 29 October 2023 [Online]. Available: https://api.semanticscholar.org/CorpusID:13022315
  • [14] J. Kulisz, J. Mikucki, "An IP-Core Generator for Circuits Performing Arithmetic Multiplication", IFAC Proceedings Volumes, vol. 46, i. 28, 2013, doi: https://doi.org/10.3182/20130925-3-CZ-3023.00006
  • [15] A. J. Al-Khalili, Digital Design and Synthesis Lecture Notes (2019), Accessed : 29 October 2023 [Online]. Available: https://users.encs.concordia.ca/~asim/COEN_6501/elec650.html
  • [16] S. Mishra and M. Pradhan, "Implementation of Karatsuba Algorithm Using Polynomial Multiplication", Indian Journal of Computer Science and Engineering, ISSN: 0976-5166, vol. 3, no. 1, pp 88 - 93, 2012.
  • [17] R. T. Kneusel, Numbers and Computers, Springer, USA, pp. 136, 2015, ISBN: 978-3-319-17260-6

Yıl 2023, Cilt: 6 Sayı: 3, 208 - 217, 31.12.2023

Kenan Baysal Deniz Taşkın

https://doi.org/10.35377/saucis...1229353

Öz

Kaynakça

  • [1] R. W. Keyes., "Physical Limits of Silicon Transistors and Circuits", Reports on Progress in Physics, vol. 68, no. 12, 2005, doi: 10.1088/0034-4885/68/12/R01
  • [2] B. Parhami, Computer Arithmetic Algorithms and Hardware Designs Secon Edition, Oxford University Press, New York USA, 2010, ISBN 978-0-19-532848-6
  • [3] A. A. H. Abd-Elkader, M. Rashdan, E. A. M. Hasaneen and H. F. A. Hamed, "Efficient implementation of Montgomery modular multiplier on FPGA," Computers and Electrical Engineering, vol. 97, 2022, doi: https://doi.org/10.1016/j.compeleceng.2021.107585
  • [4] A. Behl, A. Gokhale, N. Sharma, "Design and Implementation of Fast Booth-2 Multiplier on Artix FPGA", Procedia Computer Science, vol. 173, pp. 140-148, 2020, doi: https://doi.org/10.1016/j.procs.2020.06.018
  • [5] R. K. Sakali, S. Veeramachaneni, N. M. Sk, "Preferential fault-tolerance multiplier design to mitigate soft errors in FPGAs", Integration, vol. 93, 2023, doi: https://doi.org/10.1016/j.vlsi.2023.102068
  • [6] L. Malathi, A. Bharathi, A.N. Jayanthi, "FPGA design of FFT based intelligent accelerator with optimized Wallace tree multiplier for image super resolution and quality enhancement", Biomedical Signal Processing and Control, vol. 88, part B, 2024, doi: https://doi.org/10.1016/j.bspc.2023.105599
  • [7] V. Bianchi, I. D. Munari, "A modular Vedic multiplier architecture for model-based design and deployment on FPGA platforms", Microprocessors and Microsystems, vol. 76, 2020, doi: https://doi.org/10.1016/j.micpro.2020.103106
  • [8] E. Özcan, S. S. Erdem, "A fast digit based Montgomery multiplier designed for FPGAs with DSP resources", Microprocessors and Microsystems, vol 62, pp. 12-19, 2018, doi: https://doi.org/10.1016/j.micpro.2018.06.015
  • [9] M. Morales-Sandoval, C. Feregrino-Uribe, P. Kitsos, R. Cumplido, "Area/performance trade-off analysis of an FPGA digit-serial GF(2m) Montgomery multiplier based on LFSR”, Computers & Electrical Engineering, vol. 32, i. 2, pp. 542-549, 2013, doi: https://doi.org/10.1016/j.compeleceng.2012.08.010
  • [10] R. S. Özbey and A. Sertbaş, "Klasik Çarpma Algoritmalarının Donanımsal Simülasyonları ve Performans Değerlendirimi", Inter. Conf. on Electrical and Electronics Engineering (ELECO 2004), pp. 303-308, 2004
  • [11] A. D. Booth, "A Signed Binary Multiplication Technique", The Quarterly Journal of Mechanics and Applied Mathematics. Math. Oxford University Press, vol. 4, no. 2, pp. 236-240, 1951, doi: https://doi.org/10.1093/qjmam/4.2.236
  • [12] C. S. Wallace, "A Suggestion for a Fast Multiplier", IEEE Transactions on Electronic Computers, vol. 13, no. 1, pp. 14-17, 1964, doi: 10.1109/PGEC.1964.263830
  • [13] M. R. Kumar and G. P. Rao, " Design and Implementation Of 32 Bit High Level Wallace Tree Multiplier", International Journal of Technical Research and Applications, vol. 1, no. 4, pp. 86 - 90, 2013, Accessed : 29 October 2023 [Online]. Available: https://api.semanticscholar.org/CorpusID:13022315
  • [14] J. Kulisz, J. Mikucki, "An IP-Core Generator for Circuits Performing Arithmetic Multiplication", IFAC Proceedings Volumes, vol. 46, i. 28, 2013, doi: https://doi.org/10.3182/20130925-3-CZ-3023.00006
  • [15] A. J. Al-Khalili, Digital Design and Synthesis Lecture Notes (2019), Accessed : 29 October 2023 [Online]. Available: https://users.encs.concordia.ca/~asim/COEN_6501/elec650.html
  • [16] S. Mishra and M. Pradhan, "Implementation of Karatsuba Algorithm Using Polynomial Multiplication", Indian Journal of Computer Science and Engineering, ISSN: 0976-5166, vol. 3, no. 1, pp 88 - 93, 2012.
  • [17] R. T. Kneusel, Numbers and Computers, Springer, USA, pp. 136, 2015, ISBN: 978-3-319-17260-6
Toplam 17 adet kaynakça vardır.

Ayrıntılar

Birincil Dil İngilizce
Konular Yazılım Mimarisi
Bölüm Makaleler
Yazarlar

Kenan Baysal 0000-0002-2205-7185

Deniz Taşkın 0000-0001-7374-8165

Erken Görünüm Tarihi 27 Aralık 2023
Yayımlanma Tarihi 31 Aralık 2023
Gönderilme Tarihi 4 Ocak 2023
Kabul Tarihi 7 Kasım 2023
Yayımlandığı Sayı Yıl 2023Cilt: 6 Sayı: 3

Kaynak Göster

IEEE K. Baysal ve D. Taşkın, “High-Capacity Data Processing with FPGA-Based Multiplication Algorithms and the Design of a High-Speed LUT Multiplier”, SAUCIS, c. 6, sy. 3, ss. 208–217, 2023, doi: 10.35377/saucis...1229353.
 Kapak Resmi İndir

    Sakarya University Journal of Computer and Information Sciences in Applied Sciences and Engineering: An interdisciplinary journal of information science